d a t a sh eet product speci?cation file under integrated circuits, ic04 january 1995 integrated circuits hef4737b hef4737v lsi quadruple static decade counters for a complete data sheet, please also download: the ic04 locmos he4000b logic family specifications hef, hec the ic04 locmos he4000b logic package outlines/information hef, hec
january 1995 2 philips semiconductors product speci?cation quadruple static decade counters hef4737b hef4737v description the hef4737b and hef4737v are static quadruple decade counters for frequencies from 0 to 10 mhz. the counters are supplied with an extra overload flip-flop giving a total count capability of 19 999. the counter has the following inputs and outputs: a count input (cp), an asynchronous reset input (mr), an asynchronous preset input (pl), a transfer input (t), an output enable input (eo) (which controls the bcd outputs), the digit select inputs (s a , s b , s c ) (which perform selection of the contents of the latches to the 3-state bcd outputs (o 0 to o 3 )), and the carry outputs (co 2 to co 5 ) (which give the carry signals of the decades except from the first decade). the complementary mos structure gives the devices very low stand-by and operating dissipation. operating from a single supply voltage all outputs can drive one standard ttl input without interface circuitry under all specified operating conditions. the bcd digit outputs are locmos 3-state outputs. the high impedance off-state feature allows common busing of the outputs. the counters are supplied with asynchronous reset and preset to 19 999 facilities making them suitable for counter and time base applications. all carry signals are available except from the first decade. schmitt-trigger action in the inputs makes the circuit highly tolerant to slower input rise and fall times. recommended supply voltage range for hef4737b is 3 to 15 v and for hef4737v is 4,5 to 12,5 v. pinning cp count input mr asynchronous reset input pl asynchronous preset input t transfer input s a , s b , s c digit select inputs eo output enable input o 0 to o 3 bcd outputs co 2 to co 5 carry outputs fig.1 pinning diagram. supply voltage family data, i dd limits category lsi see family specifications hef4737bp; HEF4737VP(n); 18-lead dil plastic (sot102-1) hef4737bd; hef4737vd(f); 18-lead dil ceramic (sot133b) ( ): package designator north america rating recommended operating hef4737b - 0,5 to 18 3,0 to 15,0 v hef4737v - 0,5 to 18 4,5 to 12,5 v
january 1995 3 philips semiconductors product speci?cation quadruple static decade counters hef4737b hef4737v fig.2 block diagram. functional description input signals count input (cp) the signal to be counted is applied to this input. when pl and mr are low the contents of the counter increments by one at a low to high transition of cp. reset input (mr) this is an asynchronous reset. a high level applied to this input will reset the counter to zero independent of the level at the count input and preset input. preset input (pl) this is an asynchronous preset. when mr is low a high at the pl input will preset the counter to 19 999 independent of the level at the count input. transfer input (t) a high level applied to this input allows the information held by the counter to pass to the latches. output enable input (eo) a high level at this input enables the bcd outputs and information can be read out of the latches using the
january 1995 4 philips semiconductors product speci?cation quadruple static decade counters hef4737b hef4737v multiplexer. a low level at this input disables the bcd outputs making them floating (high impedance off-state). digit select inputs (s a , s b , s c ) notes 1. h = high state (the more positive voltage) 2. l = low state (the less positive voltage) 3. x = state is immaterial 4. when d5 is selected, the contents of d5 is available at o 0 and o 1 ,o 2 and o 3 are low. 5. lsd = least significant divider 6. msd = most significant divider s a s b s c l l l selects d1 (lsd) h l l selects d2 l h l selects d3 h h l selects d4 x x h selects d5 (msd) output signals the carry outputs are active low outputs. carry output co 2 when the contents of the first two decades of the counter are both 9 then the co 2 output becomes low. it remains low until the next low to high transition of the count input, i.e. until the contents of the first two decades are zero. co 2 is low when the contents of the counter are: 00 099, 00 199, 00 299 etc. carry output co 3 when the contents of the first three decades of the counter are all 9 then the co 3 output becomes low. it remains low until the next low to high transition of the count input, i.e. until the contents of the first three decades are zero. co 3 is low when the contents of the counter are 00 999, 01 999, 02 999 etc. carry output co 4 when the contents of the first four decades of the counter are all 9 then the co 4 output becomes low. it remains low until the next low to high transition of the count input, i.e. until the contents of the first four decades are zero. co 4 is low when the contents of the counter are 09 999 and 19 999. the carry signals co 2 , co 3 and co 4 are suppressed while the preset is active. a high to the preset input sets the counter to 19 999 but the carry signals remain high until preset input returns to low, then the carry outputs will also become low. carry output co 5 when the content of the counter is 10 000 the co 5 output becomes low. it returns to high when the content of the counter is zero. digit outputs (o 0 to o 3 ) the digit outputs give the contents of the selected latch. the output is in the form of bcd, positive logic.
january 1995 5 philips semiconductors product speci?cation quadruple static decade counters hef4737b hef4737v this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... fig.3 timing diagram.
january 1995 6 philips semiconductors product speci?cation quadruple static decade counters hef4737b hef4737v the values given at v dd = 15 v in the following d.c. and a.c. characteristics, are not applicable to the hef4737v, because of its reduced supply voltage range. dc characteristics v ss =0v ac characteristics v ss =0v; t amb =25 c; c l = 15 pf; input transition times 20 ns v dd v v oh v v ol v symbol t amb ( c) - 40 + 25 + 85 min. max. min. max. min. max. input leakage current at 10 i in -- - 0,3 - 1 m a v i = 0 or v dd 15 -- - 0,3 - 1 m a output (sink) 4,75 0,4 1,6 - 1,6 - 1,4 - ma current low 10 0,5 i ol 2,5 - 2,3 - 1,7 - ma 15 1,5 7,0 - 6,0 - 4,0 - ma output (source) 5 4,6 0,96 - 0,80 - 0,65 - ma current high 10 9,5 - i oh 2,4 - 2,0 - 1,6 - ma 15 13,5 7,0 - 6,0 - 4,5 - ma output (source) current high 5 2,5 - i oh 3,0 - 2,5 - 2,0 - ma 3-state output leakage current 10 i oz - 1,6 - 1,6 - 12 m a v o = 0 or v dd 15 - 1,6 - 1,6 - 12 m a v dd v symbol min. typ. max. typical extrapolation formula propagation delays cp ? o n 5 320 640 ns 308 ns + (0,24 ns/pf) c l (d1 selected) 10 t phl 120 240 ns 125 ns + (0,10 ns/pf) c l high to low 15 90 180 ns 86 ns + (0,07 ns/pf) c l 5 320 640 ns 296 ns + (0,48 ns/pf) c l low to high 10 t plh 120 240 ns 110 ns + (0,20 ns/pf) c l 15 90 180 ns 82 ns + (0,15 ns/pf) c l cp ? o n 5 620 1240 ns 608 ns + (0,24 ns/pf) c l (d5 selected) 10 t phl 330 660 ns 325 ns + (0,10 ns/pf) c l high to low 15 250 500 ns 246 ns + (0,07 ns/pf) c l 5 620 1240 ns 596 ns + (0,48 ns/pf) c l low to high 10 t plh 330 660 ns 320 ns + (0,20 ns/pf) c l 15 250 500 ns 242 ns + (0,15 ns/pf) c l
january 1995 7 philips semiconductors product speci?cation quadruple static decade counters hef4737b hef4737v cp ? co 2 5 220 440 ns 208 ns + (0,24 ns/pf) c l high to low 10 t phl 110 220 ns 105 ns + (0,10 ns/pf) c l 15 85 170 ns 81 ns + (0,07 ns/pf) c l 5 220 400 ns 196 ns + (0,48 ns/pf) c l low to high 10 t plh 110 220 ns 100 ns + (0,20 ns/pf) c l 15 85 170 ns 77 ns + (0,15 ns/pf) c l propagation delays cp ? co 5 5 350 700 ns 338 ns + (0,24 ns/pf) c l high to low 10 t phl 160 320 ns 155 ns + (0,10 ns/pf) c l 15 120 240 ns 116 ns + (0,07 ns/pf) c l 5 350 700 ns 326 ns + (0,48 ns/pf) c l low to high 10 t plh 160 320 ns 150 ns + (0,20 ns/pf) c l 15 120 240 ns 112 ns + (0,15 ns/pf) c l s n ? o n 5 200 400 ns 188 ns + (0,24 ns/pf) c l high to low 10 t phl 80 160 ns 75 ns + (0,10 ns/pf) c l 15 55 110 ns 51 ns + (0,07 ns/pf) c l 5 200 400 ns 176 ns + (0,48 ns/pf) c l low to high 10 t plh 80 160 ns 70 ns + (0,20 ns/pf) c l 15 55 110 ns 47 ns + (0,15 ns/pf) c l t ? o n 5 220 440 ns 208 ns + (0,24 ns/pf) c l high to low 10 t phl 90 180 ns 85 ns + (0,10 ns/pf) c l 15 60 120 ns 56 ns + (0,07 ns/pf) c l 5 220 440 ns 196 ns + (0,48 ns/pf) c l low to high 10 t plh 90 180 ns 80 ns + (0,20 ns/pf) c l 15 60 120 ns 52 ns + (0,15 ns/pf) c l mr ? o n 5 490 980 ns 478 ns + (0,24 ns/pf) c l high to low 10 t phl 200 400 ns 195 ns + (0,10 ns/pf) c l 15 60 120 ns 56 ns + (0,07 ns/pf) c l pl ? o n 5 260 520 ns 236 ns + (0,48 ns/pf) c l low to high 10 t plh 110 220 ns 100 ns + (0,20 ns/pf) c l 15 85 170 ns 77 ns + (0,15 ns/pf) c l mr ? co n 5 350 700 ns 326 ns + (0,48 ns/pf) c l low to high 10 t plh 160 320 ns 150 ns + (0,20 ns/pf) c l 15 120 240 ns 112 ns + (0,15 ns/pf) c l pl ? co n 5 350 700 ns 338 ns + (0,24 ns/pf) c l high to low 10 t phl 160 320 ns 155 ns + (0,10 ns/pf) c l 15 120 240 ns 116 ns + (0,07 ns/pf) c l v dd v symbol min. typ. max. typical extrapolation formula
january 1995 8 philips semiconductors product speci?cation quadruple static decade counters hef4737b hef4737v output transition 5 35 70 ns 15 ns + (0,40 ns/pf) c l times; any output 10 t thl 18 36 ns 9 ns + (0,18 ns/pf) c l high to low 15 15 30 ns 8 ns + (0,13 ns/pf) c l 5 50 100 ns 15 ns + (0,70 ns/pf) c l low to high 10 t tlh 30 60 ns 13 ns + (0,33 ns/pf) c l 15 25 50 ns 13 ns + (0,23 ns/pf) c l 3-state propagation delays output disable times eo ? o n 5 60 120 ns high 10 t phz 35 70 ns 15 25 50 ns 5 60 120 ns low 10 t plz 35 70 ns 15 25 50 ns output enable times eo ? o n 5 90 180 ns high 10 t pzh 40 80 ns 15 30 60 ns 5 90 180 ns low 10 t pzl 40 80 ns 15 30 60 ns maximum cp pulse 5 160 80 ns width; low 10 t wcpl 60 30 ns 15 50 25 ns minimum mr pulse 5 100 50 ns width; high 10 t wmrh 50 25 ns 15 40 20 ns minimum pl pulse 5 120 60 ns width; high 10 t wplh 60 30 ns 15 50 25 ns minimum t pulse 5 100 50 ns width; high 10 t wth 40 20 ns 15 36 18 ns maximum clock 5 3 6 mhz pulse frequency 10 f max 8 16 mhz 15 10 20 mhz v dd v symbol min. typ. max. typical extrapolation formula
january 1995 9 philips semiconductors product speci?cation quadruple static decade counters hef4737b hef4737v v dd v typical formula for p ( m w) dynamic power 5 950 f i +? (f o c l ) v dd 2 where dissipation per 10 4 200 f i +? (f o c l ) v dd 2 f i = input freq. (mhz) package (p) 15 11 200 f i +? (f o c l ) v dd 2 f o = output freq. (mhz) c l = load cap. (pf) ? (f o c l ) = sum of outputs v dd = supply voltage (v)
|
